6.17 System Interface Request and Response Protocol
External Response Protocol
The processor supports two classes of external responses:
- external data responses provide a double/single/partial-word of data or provide a block of data using the SysAD[63:0] bus
- external completion responses provide an acknowledge, error, or negative acknowledge indication using the SysResp[4:0] bus
An external agent may only issue an external data response to the processor when the System interface is in slave state. If the System interface is not already in slave state, the external agent must first negate SysGnt* and then wait for the processor to assert SysRel*. If the System interface is already in slave state, the external agent may issue an external data response immediately.
External data responses may be accepted by the processor in adjacent SysClk cycles and in arbitrary order, relative to corresponding processor requests.
An external agent may issue an external completion response when the System interface is in either master or slave state. External completion responses may be accepted by the processor in adjacent SysClk cycles and in arbitrary order, relative to the corresponding processor requests.
An external agent may issue an external block data response in response to a processor block read or upgrade request.
An external agent issues an external block data response with 8 or 16 data cycles. Each data cycle consists of the following:
The first 7 or 15 data cycles have a response data type indication, and the last data cycle has a response last data type indication. The external agent may negate SysVal* between data cycles of an external block data response.
External block data response data must be supplied in subblock order, beginning with the quadword-aligned address specified by the corresponding processor request.
External block data responses for processor coherent block read shared or noncoherent block read requests may indicate a state of Shared, CleanExclusive, or DirtyExclusive. External block data responses for processor coherent block read exclusive or upgrade requests may indicate a state of CleanExclusive or DirtyExclusive.
Figure 6-17 depicts two processor block read requests and the corresponding external block data responses.
Figure 6-17 External Block Data Response Protocol
An external agent may issue an external double/single/partial-word data response in response to a processor double/single/partial-word read request.
An external agent issues an external double/single/partial-word data response with a single data cycle; the data cycle consists of:
Figure 6-18 depicts a processor double/single/partial-word read request and the corresponding external double/single/partial-word data response.
Figure 6-18 External Double/Single/Partial-Word Data Response Protocol
An external agent issues an external completion response to provide an acknowledge, error, or negative acknowledge to an outstanding request, and to free the associated request number.
An external agent issues an external completion response by driving the response on SysResp[4:0] and asserting SysRespVal* for one SysClk cycle. SysResp[4:2] contains the request number associated with the corresponding outstanding request and SysResp[1:0] contains an acknowledge, error, or negative acknowledge indication, as described below:
An external ERR or NACK completion response issued in response to an external intervention, allocate request number, or invalidate has no affect on the processor except to free the request number.
Figure 6-19 depicts a processor upgrade request and a corresponding external completion response.
Figure 6-19 External Completion Response Protocol
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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